1) Field of the Invention
The present invention relates to data communication system and method with a data scrambling, and more particularly to an improvement of data communication system and method which perform a digital data array configuration change according to a certain scramble function to carry out a secret communication.
2) Description of the Related Arts
Conventionally, a wireless transmission or a transference of various data is carried out for processing the data, it is sometimes necessary to substantially conceal such data.
In such a case, for example, it is useful to prevent a tapping of conversation data in a radio telephone communication, and it is preferable to perform a certain kind of modulation of the conversation data in order not to be understood by an interceptor even when the conversation data to be transmitted by an electric wave are intercepted.
Also, when an ID number of a cash card of a bank or the like can be readily read out by the third party, the safety of the cash card can not be held, and in such a case, it is also preferable to prevent an analysis or decoding of the card data without using a particular read key or password.
Further, in the near future, the spread of an IC card is realized and in certain cases, an ID number for a bank account is written or much other private information considered to be secret is recorded in the card. In order to prevent the ready reading of the private information from the IC card, it is preferable to record the data in the card after the above-described modulation of the data contents.
Accordingly, at the data communication or transference, it is desired to perform the radio or data communication or data recording is performed while the data are made secret as described above.
In the data modulation of this kind, in case of digital data to be handled, the modulated data can be relatively readily made secret, and a simplest and most effective modulation is known as a data scrambling. A principle of a conventional system capable of applying to this scramble modulation will be described hereinbelow.
In FIG. 5, there is shown a data scrambling system using the principle of a conventional data encryption system, for example, a FEAL-8 cipher algorithm, as disclosed in "Fast Data Encipherment Algorithm FEAL-8" by Miyaguchi, Shiraishi and Shimizu, NTT Research Practicing Report, Volume 37, Nos. 4 to 5, 1988. In the drawing, numerals 13 and 14 denote 8 bytes of plaintext and 8 bytes of scrambled text, respectively, and the data scrambling system includes a plurality of processing blocks (PBs) 15, 16, 17 and 18 for converting an input signal by using a part of extended keys as a parameter to output a converted signal, a plurality of exclusive logical ORs 21 and a magnification key latch 22 for storing 32 bytes of extended keys.
Next, the operation of the data scrambling system shown in FIG. 5 will now be described. First, an exclusive OR of the input plaintext 13 and the 8 bytes from the 0 byte to the 7 byte of the extended key output from the extended key latch 22 is calculated, and then the exclusive OR of the insignificant 4 bytes and the significant 4 bytes of the calculation result is calculated to output the calculation result to the next step.
Then, the insignificant 4 bytes of the previous step output are input to the processing block 15 and the processing block 15 converts the input signal by using the two bytes from the 8 byte to the 9 byte of the magnification key output from the extended key latch 22 as a parameter to output a converted signal. The exclusive OR of the output of the processing block 15 and the significant 4 bytes of the previous step output is calculated, and the significant 4 bytes and the insignificant 4 bytes of the calculation result are replaced with each other to output the obtained signal to the next step.
Next, the insignificant 4 bytes of the previous step output is input to the processing block 16 and the processing block 16 converts the input signal by using the two bytes from the 10 byte to the 11 byte of the magnification key output from the extended key latch 22 as the parameter to output a converted signal. The exclusive OR of the output of the processing block 16 and the significant 4 bytes of the previous step output is calculated, and the significant 4 bytes and the insignificant 4 bytes of the calculation result are replaced with each other to output the obtained signal to the next step.
Then, the same operation as described above is repeated eight times to the processing block 18. Next, after the significant 4 bytes and the insignificant 4 bytes of the calculation result are replaced with each other, the exclusive OR of the significant 4 bytes and the insignificant 4 bytes is calculated. Further, the exclusive OR of the calculation result and the 8 bytes from the 24 byte to the 31 byte of the extended key output from the extended key latch 22 is calculated to output the scrambled text 14.
In FIG. 6, there is shown a data scrambling system using the principle of another conventional data encryption system, for example, a MULTI-2 cipher algorithm, as disclosed in "Multi-Media Encryption Algorithm", by Takaragi, Sasaki and Nakagawa, Multimedia Communication and Dispersed Processing, 40-5, 1989. In the drawing, numerals 13 and 14 denote a 64 bits of plaintext and a 64 bits of scrambled text, respectively, and the data scrambling system has the same construction as the above-described data scrambling system shown in FIG. 5 except processing blocks (PBs) 15, 16, 17, 18, 19 and 20.
Next, the operation of the data scrambling system shown in FIG. 6 will now be described. First, the input plaintext 13 is divided into significant 32 bits and insignificant 32 bits, and the exclusive OR of the significant 32 bits and the insignificant 4 bits is calculated to output a first calculation result to the processing block 15. The processing block 15 converts the input signal by using the 32 bits from the 0 bit to the 31 bit of the extended key output from the extended key latch 22 as the parameter to output a converted signal. The exclusive OR of the output of the processing block 15 and the significant 32 bits is calculated to output a second calculation result to the processing block 16, and the processing block 16 converts the input signal by using the 64 bits from the 32 bit to the 95 bit of the extended key output from the extended key latch 22 as the parameter to output a converted signal. The exclusive OR of the output of the processing block 16 and the first calculation result of the above-described exclusive OR is calculated to output a third calculation result to the processing block 17, and the processing block 17 converts the input signal by using the 32 bits from the 96 bit to the 127 bit of the extended key output from the extended key latch 22 as the parameter to output a converted signal. The exclusive OR of the output of the processing block 17 and the second calculation result of the above-described exclusive OR is calculated to output a fourth calculation result.
Then, the exclusive OR of the third and fourth calculation results of the above-described exclusive ORs is calculated to output a fifth calculation result to the processing block 18, and the processing block 18 converts the input signal by using the 32 bits from the 128 bit to the 159 bit of the extended key output from the extended key latch 22 as the parameter to output a converted signal. The exclusive OR of the output of the processing block 18 and the fourth calculation result of the above-described exclusive OR is calculated to output a sixth calculation result to the processing block 19, and the processing block 19 converts the input signal by using the 64 bits from the 160 bit to the 223 bit of the extended key output from the extended key Iatch 22 as the parameter to output a converted signal. The exclusive OR of the output of the processing block 19 and the fifth calculation result of the above-described exclusive OR is calculated to output a seventh calculation result to the processing block 20, and the processing block 20 converts the input signal by using the 32 bits from the 224 bit to the 255 bit of the extended key output from the extended key latch 22 as the parameter to output a converted signal. The exclusive OR of the output of the processing block 20 and the sixth calculation result of the above-described exclusive OR is calculated to output an eighth calculation result, and the eighth calculation result and the seventh calculation result as the significant 32 bits and the insignificant 32 bits are combined to output the scrambled text 14.
Further, another conventional data scrambling system has been proposed, as disclosed in Japanese Patent Laid-Open No. Sho 62-81145. In this case, input data are divided into a plurality of processing blocks, and the positional order configuration change of the processing blocks can be determined by both the input data and a scrambling key. However, in this case, it takes a long time to perform a descrambling.
As described above, in the conventional data scrambling systems, the address of the extended key input to each processing block from the extended key latch 22 is fixed, and hence an interceptor can readily analyze or decode the extended key in a communication path to which a chosen plaintext attack can be conducted.
Furthermore, as described above, in the conventional data scrambling systems, the order of the processing blocks is fixed, and thus the interceptor can analyze all of the extended key in the communication path to which the chosen plaintext attack can be conducted.